The present invention relates generally to integrated circuits and, more particularly, to a D-type flip-flop circuit.
FIG. 1 illustrates a conventional 24-transistor transmission gate flip-flop (TGFF) 100. The conventional TGFF 100 has eight inverters I1 to I8 and four transmission gates T1 to T4. Inverters I1, I4 and I5 and transmission gates T1 and T2 make up a master latch 110, while inverters I6, I7 and I8 and transmission gates T3 and T4 make up a slave latch 120. Two inverters I2 and I3 form a clock circuit for generating control signals CLKN and CLKI from a clock signal CLK for controlling the transmission gates T1 to T4.
When the clock signal CLK transitions to a low level, the first control signal CLKN goes high and the second control signal CLKI goes low. As a result, transmission gates T1 and T4 are turned on (i.e., become ‘transparent’ to signals at their inputs). Meanwhile transmission gates T2 and T3 are turned off (i.e., become ‘impervious’ to signals received at their inputs). Accordingly, when the clock signal CLK is low, the master latch 110 is in a transparent mode and new data is passed from the input D through inverter I1, transmission gate T1, inverter I4 and inverter I5 to the output of inverter I5. Conversely, the slave latch 120 is in a hold mode and the previous data is held in the slave latch 120 within the transmission gate T4 and inverters I6 and I7.
When the clock signal CLK transitions to a high level, the first control signal CLKN goes low and the second control signal CLKI goes high. As a result, transmission gates T2 and T3 are turned on, whereas the transmission gates T1 and T4 are turned off. Accordingly, when the clock signal CLK is high, the master latch 110 is in a hold mode and the new data received at the input D is held in the master latch 110 within inverters I4, I5 and transmission gate T2. Conversely, the slave latch 120 is in a transparent mode, and the new data held within the master latch 110 is passed to the output Q through transmission gate T3 and inverters I6 and I8.
The conventional TGFF 100 is robust over a wide operating supply voltage range. However, the conventional TGFF 100 has a large number of clocked nodes (two per transmission gate). Voltage signals at these clocked nodes always toggle with the clock signal CLK, irrespective of the data at the input D. Such toggling of internal nodes within the TGFF 100 consumes power. Significantly, each of the clocked nodes within the conventional TGFF 100 toggles in response to each transition of the clock signal CLK, even when the data at input D does not change. Accordingly, the conventional TGFF 100 consumes a significant amount of power as a result of the toggling of the clocked nodes, even when the data at the input D does not change.
FIG. 2 illustrates a static contention-free single-phase-clocked 24-transistor flip-flop (SSC-FF) 200, disclosed in the 2014 IEEE International Solid-State Circuits Conference (Y. Kim, et al., “A static Contention-Free Single-Phase-Clocked 24T Flip-Flop in 45 nm for Low Power Applications”, ISSCC Dig. Tech. Papers, pp. 466-467, 2014).
For the SSC-FF 200, when the clock signal CLK goes low, an internal control node net1 goes high. The transistors M2 and M3 are turned on to pass the new data received at the input D to the output of the inverter M11/M12. Inverter M11/M12 forms part of a master latch, along with transistors M5 and M7. At the same time, M19 and M22 are on to keep the previous data in the slave latch, which comprises transistors M17, M18, M19, M20, M21 and M22.
When the clock signal CLK goes high, if the new data at the input D is low, the internal control node net1 goes low and keeps the new data in the master latch using transistor M5. In addition, a low internal control node net1 causes transistor M13 to be on, pulling node QN high and thus causing the output Q to go low via inverter M23/M24.
Conversely, if the clock signal CLK goes high when the new data at the input D is high, internal control node net1 is kept high through transistor M6. The data is held in the master latch by inverter M11/M12 and transistors M7 and M10. Meanwhile, transistors M14, M15 and M16 are turned on and pull node QN low, causing the output Q to go high via inverter M23/M24.
The SSC-FF 200 uses a clock-gate implementation including transistors M6, M8, M9, and M10 to avoid toggling of the internal control node net1 when the data at the input D is high. As a result, the SSC-FF 200 achieves lower power dissipation than the conventional TGFF 100 illustrated in FIG. 1 during periods when the input data stays high. However, the SSC-FF 200 suffers from the same high power dissipation as the conventional TGFF 100 when the input data stays low.